Recently, in the signal transmission between equipments, a system using a high-speed serial signal with small amplitude has been adopted. This system makes it possible, as compared with the technique wherein the digital signal is transmitted in parallel, to reduce electromagnetic interference (EMI) caused in the course of digital signal transmission, in addition to a requirement for only a small number of cables.
In order to achieve a high-speed serial communication, there is provided at the transmitting side a parallel-serial conversion circuit, which synchronizes with a base clock signal to convert parallel data into serial data by using sub clock signals with multi-phases (in this application, referred to as multi-phase clock signals) having a phase difference of equal intervals. Therefore there arises a need to provide a multi-phase clock generating circuit that generates the multi-phase clock signals and supply the multi-phase clock signals to the parallel-serial conversion circuit.
As the multi-phase clock generating circuit, there is used, for example, a voltage or current controlled differential ring oscillator circuit, which is constructed of multi-stage delay differential inverting amplification circuits connected to each other in the form of a ring. By using the differential ring oscillator circuit as described above, multi-phase clock signals having phase difference with equal intervals can be easily extracted from the multi-stage delay differential inverting amplification circuits. In order to generate the multi-phase clock signals having phase difference of precisely equal intervals from high-speed differential ring oscillator circuit, it is necessary to equalize the loads of the multi-stage delay differential inverting amplification circuits and also to equalize the stray capacitances of the multiple-phase clock signal wirings.
Conventionally, in order to equalize the load of each stage of delay differential inverting amplification circuits, N-stage delay differential inverting amplification circuits, which constitutes the differential ring oscillator circuit, are disposed in two rows on a semiconductor substrate, and in each row, there is made such an arrangement that the successive delay differential inverting amplification circuits are disposed adjacent to each other. By virtue of this arrangement, it is made possible to minimize the delay in the wirings between the output of one circuit and the input of the next circuit of the N-stage delay differential inverting amplification circuits, and to achieve a differential ring oscillator circuit capable of oscillating at a high frequency.
However, in the differential ring oscillator circuit that outputs multi-phase clock signals having phase difference of equal intervals and is required for achieving the high speed serial communication, multi-phase clock signals are generally extracted from the outputs of the alternate delay differential inverting amplification circuits. Accordingly, signals are extracted from each row of the delay differential inverting amplification circuits disposed in two rows. Consequently, according to the conventional arrangement and wirings, the length of the wirings for the multi-phase clock signals of one row becomes longer than that of another row, and therefore, there arises a difficulty to make uniform all stray capacitances of the multiple-phase clock signal wirings. Also, the layout of the multiple-phase clock signal wirings has to be made in a relatively wide area in the periphery of the differential ring oscillator circuit. For this reason, there arises such problem that the area of the semiconductor substrate becomes larger.